A plethora of applications exist for effecting electrical contact between two conductors. One significant application is effecting interconnection between the leads of an integrated circuit device and conductive pads or terminals on a printed circuit board which serves to effect an interfacing between the integrated circuit (IC) device and a tester apparatus. Such apparatus are used to evaluate performance of integrated circuit devices.
Numerous considerations bear upon the structure employed to interconnect the IC and the printed circuit board. These factors include both electrical and mechanical considerations. For typical interconnection systems, special attention must be given to the electrical performance including self inductance and capacitance, the life span requirements, the repairability or replacability, the operation temperature environment, the coplanarity of the device terminals, the mechanical manufacturing limitations, and the device alignment and orientation of the device terminals relative to the interconnection system.
In a typical semi-conductor production facility, each integrated circuit is tested using a tester apparatus. The tester apparatus may be connected to an interconnection system wherein the leads of an integrated circuit are connected to a PC board within the interconnection system. The PC board may then be controlled by the tester apparatus for testing the integrated circuit.
The tester apparatus may test the functionality and performance of an integrated circuit through the interconnection system. Due to manufacturing process variations, a portion of the integrated circuits may perform at a higher level than other integrated circuits. Therefore, the tester apparatus may be used to sort the devices according to their performance characteristics. This is termed "speed grading". Typically, the higher performance integrated circuits will receive a premium price in the market place. It can readily be seen that it is important that the interconnection system not distort the performance characteristics of the integrated circuit under test. If it does, a substantial amount of revenue may be lost by the integrated circuit manufacturer.
A main objective of an interconnection system is to maintain a "non-distorting electrical interconnection" between the tester apparatus and the integrated circuit as discussed above. To accomplish this, it is a goal of an interconnection system to have low lead inductance/resistance, low lead-to-lead capacitance, low lead-to-ground capacitance, and a high electrical decoupling factor. These characteristics all reduce the "distorting" nature of the electrical interconnection system.
Another main objective of the interconnection system is to maintain a consistent and reliable electrical interconnection over many test cycles. In conventional interconnection systems, the contact resistance of the interconnection system may change after continued use. A main cause of this resistance change may be solder buildup on the tips of the contacts within the interconnection system. Increased contact resistance can distort the performance of the integrated circuit and thus reduce the test yield realized.
Because of tolerances in the manufacturing process, all of the leads of a semiconductor package may not be coplanar. For similar reasons, contacts of the interconnection system itself may not be fully coplanar. Therefore, when the integrated circuit and the interconnection system are brought into engagement, some of the leads of the integrated circuit package may not be adequately contacted to corresponding contacts within the interconnection system. It is a goal of the interconnection system to compensate for these non-coplanarities.
To accomplish this, the interconnection system may comprise movable interconnection contact elements such that the first integrated circuit package leads may contact and depress a corresponding contact in the interconnection system until the remaining package leads come into engagement with a corresponding contact. An advantage of this arrangement is that the movable contact elements may allow each semiconductor lead to have a force applied thereon which falls within an acceptable range to establish a gas-tight connection, despite the non-coplanarity of the semiconductor package and interconnection system.
One prior art structure which seeks to accomplish the purpose of the present invention is a pogo-pin configuration. A pogo-pin configuration typically consists of a contact tip, a shaft, a barrel, and a spring. The shaft is enclosed within the barrel and biased by the spring to an upward position. Located at the upper tip of the shaft is the contact tip for contacting the lead of a semiconductor package. The shaft generally makes electrical contact with the barrel, and the lower portion of the barrel is connected to a PC board. As a semiconductor package lead comes into contact with the contact tip, the spring allows the shaft to depress downward into the barrel while still maintaining electrical contact with the barrel. The semiconductor package is forced down on the pogo-pins until all of the semiconductor package leads have an appropriate force thereon.
Although the pogo-pin configuration solves some of the problems discussed above, the leads are generally long and therefore inject a substantial amount of inductance into the interconnection system. Because of this relatively high level of inductance, the pogo-pin configuration may generally be limited to medium to low speed applications.
Another prior art structure which seeks to accomplish the purpose of the present invention is known as the Yamaichi contact. This type of contact includes an inverted L-shaped support having a cantilevered contacting portion mounted at the distal end of the generally horizontal leg of the inverted, L-shaped support, and extending generally parallel to that leg. The distal end of the contacting portion is upwardly turned so that a point thereof is engageable by a lead of an integrated circuit device to be contacted. The support, in turn, is engaged in some manner with or through a pad or terminal portion of a printed circuit board. Problems that have been observed with the Yamaichi contact include solder buildup, difficulty of construction, and high inductance. In addition, the Yamaichi contact relies on the flexure of the contact material.
Another type of structure which seeks to accomplish the purpose of the present invention is a fuzz button contact. A fuzz button contact typically consists of a specially designed array of resilient knitted wire mesh which is retained within a housing that is mounted to a PC board. The lead of a semiconductor package may be received by the housing, wherein the wire mesh forms a connection therewith. The fuzz button contact allows for some degree of compression which helps compensate for the non-coplanarity of the semiconductor package and the interconnection system. Due to the close contact of the wire mesh, a low resistance/inductance connection can be realized between the PC board and a lead of the semiconductor device. Typical problems which may exist for the fuzz button contact include the loss of compliance of the wire mesh after continued use. Furthermore, the wires within the wire mesh may become fatigued and eventually break. Finally, the wire mesh may become undesirably deformed, particularly if the fuzz button is over compressed. All of these problems limit the reliability and life expectancy of the fuzz button contact configuration.
Another prior art structure which seeks to accomplish the purpose of the present invention is a wire contact. A wire contact consists of a contact wire which is held in place by a housing. A first end of the contact wire is in contact with a PC board. A second end of the contact wire is in contact with a lead of a semiconductor package. As the lead of the semiconductor package is forced down upon the second end of the contact wire, the center portion of the contact wire is bent in a lateral direction. The properties of the contact wire may be selected to provide the desired stiffness and deflection force.
It is to these dictates and shortcomings of the prior art that the present invention is directed. It is an improved electrical interconnecting system which addresses the dictates of the prior art and resolves problems thereof.